F4 Black Pillにはいくつか種類があり、F411CEのものもあれば、F401CC, F401CEのものもあります。その後、F411CEに続いてF401CE/F401CCを入手したので、今回はF401CCとF401CE向けにソースをフォークし、RCC関係のところだけですが本稿を挙げてみることにしました。
F401CCとF401CEはクロック関連は同じなので、以下、F401CE向けのboards/arm/stm32/weact-f401ce/include/board.hです。
$ diff -urN boards/arm/stm32/stm32f411-minimum/include/board.h boards/arm/stm32/weact-f401ce/include/board.h --- boards/arm/stm32/stm32f411-minimum/include/board.h 2021-03-16 23:33:19.400000000 +0900 +++ boards/arm/stm32/weact-f401ce/include/board.h 2021-01-09 02:52:09.000000000 +0900 @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/include/board.h + * boards/arm/stm32/weact-f401ce/include/board.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_STM32F411_MINIMUM_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_STM32F411_MINIMUM_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_WEACT_F401CE_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_WEACT_F401CE_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -39,16 +39,16 @@ /* Clocking *****************************************************************/ /* System Clock source : PLLCLK (HSE) - * SYSCLK(Hz) : 96000000 Determined by PLL config - * HCLK(Hz) : 96000000 (STM32_RCC_CFGR_HPRE) + * SYSCLK(Hz) : 84000000 Determined by PLL config + * HCLK(Hz) : 84000000 (STM32_RCC_CFGR_HPRE) * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) + * APB1 Prescaler : 2 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) * HSI Frequency(Hz) : 16000000 (nominal) - * PLLM : 4 (STM32_PLLCFG_PLLM) - * PLLN : 192 (STM32_PLLCFG_PLLN) + * PLLM : 25 (STM32_PLLCFG_PLLM) + * PLLN : 336 (STM32_PLLCFG_PLLN) * PLLP : 4 (STM32_PLLCFG_PLLP) - * PLLQ : 8 (STM32_PLLCFG_PPQ) + * PLLQ : 7 (STM32_PLLCFG_PPQ) * Flash Latency(WS) : 3 * Prefetch Buffer : OFF * Instruction cache : ON @@ -75,43 +75,47 @@ * Formulae: * * VCO input freq = PLL input clock freq/PLLM 2 <= PLLM <= 63 - * VCO output freq = VCO input freq × PLLN, 192 <= PLLN <= 432 + * VCO output freq = VCO input freq × PLLN, 168 <= PLLN <= 432 * PLL output clock freq = VCO freq / PLLP, PLLP = 2,4,6 or 8 * USB OTG FS clock freq = VCO freq / PLLQ, 2 <= PLLQ <= 15 * - * There is no config for 100 MHz and 48 MHz for usb, - * so we would like to have SYSYCLK=96MHz and we must have the USB - * clock = 48MHz - * - * PLLQ = 2 PLLP = 2 PLLN=192 PLLM=25 + * We would like to have SYSYCLK=84MHz and we must have the USB clock= 48MHz. + * Some possible solutions include: * + * PLLN=210 PLLM=5 PLLP=8 PLLQ=14 SYSCLK=84000000 OTGFS=48000000 + * PLLN=210 PLLM=10 PLLP=4 PLLQ=7 SYSCLK=84000000 OTGFS=48000000 + * PLLN=336 PLLM=8 PLLP=8 PLLQ=14 SYSCLK=84000000 OTGFS=48000000 + * PLLN=336 PLLM=16 PLLP=4 PLLQ=7 SYSCLK=84000000 OTGFS=48000000 + * PLLN=420 PLLM=10 PLLP=8 PLLQ=14 SYSCLK=84000000 OTGFS=48000000 + * PLLN=420 PLLM=20 PLLP=4 PLLQ=7 SYSCLK=84000000 OTGFS=48000000* + * * We will configure like this * * PLL source is HSE * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN - * = (25,000,000 / 25) * 192 - * = 192,000,000 + * = (25,000,000 / 25) * 336 + * = 336,000,000 * SYSCLK = PLL_VCO / PLLP - * = 192,000,000 / 2 = 96,000,000 + * = 336,000,000 / 4 = 84,000,000 * USB OTG FS and SDIO Clock * = PLL_VCO / PLLQ - * = 192,000,000 / 4 = 48,000,000 + * = 336,000,000 / 7 = 48,000,000 */ #define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(25) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(192) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(4) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_4 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) -#define STM32_SYSCLK_FREQUENCY 96000000ul +#define STM32_SYSCLK_FREQUENCY 84000000ul -/* AHB clock (HCLK) is SYSCLK (96MHz) */ +/* AHB clock (HCLK) is SYSCLK (84MHz) */ #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY #define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ -/* APB1 clock (PCLK1) is HCLK/2 (48MHz) */ +/* APB1 clock (PCLK1) is HCLK/2 (42MHz) */ #define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */ #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) @@ -130,18 +134,18 @@ #define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) #define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) -/* APB2 clock (PCLK2) is HCLK (96MHz) */ +/* APB2 clock (PCLK2) is HCLK (84MHz) */ #define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK */ #define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY -/* Timers driven from APB2 will be twice PCLK2 */ +/* Timers driven from APB2 will be PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (1*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (1*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (1*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (1*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (1*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -150,29 +154,29 @@ /* REVISIT */ -#define BOARD_TIM1_FREQUENCY STM32_PCLK2_FREQUENCY +#define BOARD_TIM1_FREQUENCY (1 * STM32_PCLK2_FREQUENCY) #define BOARD_TIM2_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) #define BOARD_TIM3_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) #define BOARD_TIM4_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) #define BOARD_TIM5_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) #define BOARD_TIM6_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) #define BOARD_TIM7_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM8_FREQUENCY STM32_PCLK2_FREQUENCY +#define BOARD_TIM8_FREQUENCY (1 * STM32_PCLK2_FREQUENCY) /* SDIO dividers. Note that slower clocking is required when DMA is disabled * in order to avoid RX overrun/TX underrun errors due to delayed responses * to service FIFOs in interrupt driven mode. These values have not been * tuned!!! * - * HCLK=96MHz, SDIOCLK=96MHz, SDIO_CK=HCLK/(238+2)=400 KHz + * HCLK=84MHz, SDIOCLK=84MHz, SDIO_CK=HCLK/(208+2)=400 KHz */ /* REVISIT */ -#define SDIO_INIT_CLKDIV (238 << SDIO_CLKCR_CLKDIV_SHIFT) +#define SDIO_INIT_CLKDIV (208 << SDIO_CLKCR_CLKDIV_SHIFT) -/* DMA ON: HCLK=96 MHz, SDIOCLK=96MHz, SDIO_CK=HCLK/(2+2)=24 MHz - * DMA OFF: HCLK=96 MHz, SDIOCLK=96MHz, SDIO_CK=HCLK/(3+2)=19.2 MHz +/* DMA ON: HCLK=84 MHz, SDIOCLK=84MHz, SDIO_CK=HCLK/(2+2)=21 MHz + * DMA OFF: HCLK=84 MHz, SDIOCLK=84MHz, SDIO_CK=HCLK/(3+2)=16.8 MHz */ /* REVISIT */ @@ -183,8 +187,8 @@ # define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) #endif -/* DMA ON: HCLK=96 MHz, SDIOCLK=96MHz, SDIO_CK=HCLK/(1+2)=32 MHz - * DMA OFF: HCLK=96 MHz, SDIOCLK=96MHz, SDIO_CK=HCLK/(3+2)=19.2 MHz +/* DMA ON: HCLK=84 MHz, SDIOCLK=84MHz, SDIO_CK=HCLK/(1+2)=28 MHz + * DMA OFF: HCLK=84 MHz, SDIOCLK=84MHz, SDIO_CK=HCLK/(3+2)=16.8 MHz */ /* REVISIT */ @@ -294,7 +298,7 @@ /* LEDs * - * The STM32F411-Minimum (aka BlackPill) has a LED on PC13 pin. + * The STM32F401-Minimum (aka BlackPill) has a LED on PC13 pin. */ /* The board has only one controllable LED */ @@ -328,4 +332,4 @@ #define BUTTON_USER_BIT (1 << BUTTON_USER) -#endif /* __BOARDS_ARM_STM32_STM32F411_MINIMUM_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_WEACT_F401CE_INCLUDE_BOARD_H */F401CEとF401CCの違いは以下の通り、RAMとFLASHのサイズが違うところだけです。
$ diff -urN boards/arm/stm32/weact-f401ce/scripts/stm32f401ce.ld boards/arm/stm32/weact-f401cc/scripts/stm32f401cc.ld
--- boards/arm/stm32/weact-f401ce/scripts/stm32f401ce.ld 2021-01-06 09:23:47.000000000 +0900
+++ boards/arm/stm32/weact-f401cc/scripts/stm32f401cc.ld 2021-03-20 00:08:34.036434500 +0900
@@ -1,5 +1,5 @@
/****************************************************************************
- * boards/arm/stm32/weact-f401ce/scripts/stm32f401ce.ld
+ * boards/arm/stm32/weact-f401cc/scripts/stm32f401cc.ld
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -18,8 +18,8 @@
*
****************************************************************************/
-/* The STM32F401CE has 512Kb of FLASH beginning at address 0x0800:0000 and
- * 96Kb of SRAM beginning at address 0x2000:0000. When booting from FLASH,
+/* The STM32F401CC has 256Kb of FLASH beginning at address 0x0800:0000 and
+ * 64Kb of SRAM beginning at address 0x2000:0000. When booting from FLASH,
* FLASH memory is aliased to address 0x0000:0000 where the code expects to
* begin execution by jumping to the entry point in the 0x0800:0000 address
* range.
@@ -27,8 +27,8 @@
MEMORY
{
- flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K
- sram (rwx) : ORIGIN = 0x20000000, LENGTH = 96K
+ flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K
+ sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
}
OUTPUT_ARCH(arm)
これ以外の変更はF103RCのソースフォークの時と同じ要領で変更しています。なお、F411CEのソースフォークと同様に、nsh, rndis, usbnsh, w25(spi)の動作確認はできています。
今回は以上です。それでは。
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